1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device including wells of different conductivity types.
2. Description of the Background Art
Semiconductor devices having many transistors integrated are used in various electrical products such as workstations and personal computers.
A conventional DRAM employed as the main memory in a personal computer will be described hereinafter with reference to FIG. 15 showing a partial sectional view thereof.
Referring to FIG. 15, a DRAM includes a P type well 2, a P type well 3, and an N type well 4 formed on a P type silicon semiconductor substrate 1. The DRAM also includes an N type well 5 formed surrounding the sidewall of P well 2, and an N type bottom N well 6 formed below P well 2. The DRAM further includes an N channel MOS transistor 7 formed at P well 2, an N channel MOS transistor 8 formed at P well 3, and a P channel MOS transistor 9 formed at N well 4.
The formation of a bottom N well in a conventional DRAM will be described with reference to FIG. 16. In the conventional DRAM of FIG. 16, the area excluding the area where bottom N well 6 is to be formed is masked by a photo resist RE prior to formation of P wells 2 and 3 and N well 4. N type ions are implanted from above P type semiconductor substrate 1 to form bottom N well 6. The boundary between the portion where photo resist RE remains and the portion where photo resist RE is removed by an exposure.cndot.development step, i.e. the sidewall of photo resist RE, has a tapered configuration. Therefore, some of the N type ions will be introduced to the surface of the area where P well 3 is to be formed. If a transistor is formed at this area where N type ions are implanted, the transistor will not have the desired characteristics. Thus, a dead space was provided where no element is formed at the range within 4 .mu.m from the boundary of bottom N well 6.